// Generated for: spectre
// Generated on: Apr 12 03:03:52 2010
// Design library name: ece3663
// Design cell name: PositiveEdgeTriggeredRegister
// Design view name: schematic
simulator lang=spectre
global 0

// Library name: Tutorial
// Cell name: TeamXORInverter
// View name: schematic
subckt TeamXORInverter VDD VSS in out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
    P0 (out in VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
    N0 (out in VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn pd=3u+wn m=mult
ends TeamXORInverter
// End of subcircuit definition.

// Library name: ece3663
// Cell name: TXGate
// View name: schematic
subckt TXGate VDD VSS N P In Out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
    P0 (Out P In VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
    N0 (In N Out VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn pd=3u+wn m=mult
ends TXGate
// End of subcircuit definition.

// Library name: ece3663
// Cell name: 2:1_MUX
// View name: schematic
subckt 2to1MUX node0 node1 VDD VSS S
parameters wp0=3u wn0=1.5u ln0=600n lp0=600n mult0=1
    I6 (VDD VSS S net10) TeamXORInverter wp=wp0 wn=wn0
    I5 (node1 S Out net10 VDD VSS) TXGate wp=wp0 wn=wn0
    I4 (node0 net10 Out S VDD VSS) TXGate wp=wp0 wn=wn0
ends 2to1MUX
// End of subcircuit definition.

// Library name: ece3663
// Cell name: PositiveLatch
// View name: schematic
subckt PositiveLatch VDD VSS CLK D Q
parameters wp1=3u wn1=1.5u ln1=600n lp1=600n mult1=1
    I1 (VDD VSS net036 net34) TeamXORInverter wp=wp1 wn=wn1
    I2 (VDD VSS net34 Q) TeamXORInverter wp=wp1 wn=wn1
    I0 (Q D net036 CLK VDD VSS) 2to1MUX wp0=wp1 wn0=wn1
ends PositiveLatch
// End of subcircuit definition.

// Library name: ece3663
// Cell name: NegativeLatch
// View name: schematic
subckt NegativeLatch VDD VSS CLK D Q
parameters wp1=3u wn1=1.5u ln1=600n lp1=600n mult1=1
    I1 (VDD VSS net037 net29) TeamXORInverter wp=wp1 wn=wn1
    I2 (VDD VSS net29 Q) TeamXORInverter wp=wp1 wn=wn1
    I0 (D Q net037 CLK VDD VSS) 2to1MUX wp0=wp1 wn0=wn1
ends NegativeLatch
// End of subcircuit definition.

// Library name: ece3663
// Cell name: PositiveEdgeTriggeredRegister
// View name: schematic
I1 (CLK net16 Q VDD VSS) PositiveLatch
I0 (CLK D net16 VDD VSS) NegativeLatch



simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
    sensfile="../psf/sens.output" checklimitdest=psf 
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
saveOptions options save=allpub
